|
SEMS
 |
|
Picture #1 – is a sample photo of an integrated circuit delayered to metal 1. The metal interconnect is aluminum and you can see the tungsten plugs that connected to metal 2. In order to clearly see the metal 1 and the poly below, the silicon oxide was carefully removed. (Courtesy of Chipworks) |
 |
|
Picture #2 – is a sample photo of the same integrated circuit delayered to metal 2. Again the oxide has been carefully removed to see both the metal 2 interconnect and the metal 1 interconnect below it. (Courtesy of Chipworks)
|
 |
|
Picture #3 – is the same integrated circuit delayered to the polysilicon level. In this photo you can clearly see the poly transistors along with the contacts to metal 1 and the source/drain diffusions. A specific recipe was used to remove the oxide that would not damage the poly or the tungsten contacts. The delayering of all 3 samples was done using the Trion Phantom RIE. (Courtesy of Chipworks) |
Papers/ Applications Notes
Aluminum Etch
Application: Failure Analysis
Trion Tool: Minilock-Phantom III RIE
“Aluminum etching is one of the most difficult processes. However, if done correctly very good etch results can be obtained. A good starting recipe for a more uniform but isotropic etching of the Al is: …” read the full article
Anisotropic Dielectric Removal vs. Sequential Removal
Application: Failure Analysis
“Depending on the desired information, DELAYERING of the integrated circuit is usually performed by either of two strategies: (a) anisotropic removal of all dielectric layers, or (b) sequential removal of all layers including conductors…” read the full article
Anisotropic Etching of Polymers
Application: Failure Analysis
Trion Tool: Phantom III RIE
“Polymers, like polyimide and SU8 can be found on a variety of devices and can have a wide range of characteristics. Anisotropic etching of polymers can be used to pattern micro imprinting devices, micro fluidic channels, and waveguides among other things. The key to clean and anisotropic etching is …” read the full article
Hybrid Reactors & Deep Oxide (Skeleton) Etch
Application: Failure Analysis
“Keeping devices active during deprocessing can be a major frustration for reliability engineers. Reactive ion etching (RIE) provides a rapid, controlled and acid-free method for delayering integrated circuits. However, RIE places a working device directly on a powered electrode, and this can produce surface contamination …” read the full article
Plasma Basics & History of Plasma Reactors
Application: Failure Analysis
“Plasma is called, by many, the fourth state of matter. It is different from the other three, in that it contains free disassociated electrons and ions in a balanced steady-state condition. This, by definition, is a plasma. A plasma contains in a disassociated state: free radicals, ions, electrons and unexcited molecules. …” read the full article
Polyimide Etch
Application: Failure Analysis
Trion Tool: Phantom III RIE
“The main problem, in the removal of polyimide, is insuring that the polyimide does not over heat during the process. If this occurs the polyimide can carbonize, leave a grass like residue, and be virtually impossible to get off. Reducing the ion bombardment solves this problem; running very low power, and/or “floating” the sample in the plasma, and/or using a hybrid reactor can accomplish this. A good starting recipe for polyimide removal is: …” read the full article
Polysilicon Etch
Application: Failure Analysis
Trion Tool: Minilock-Phantom III RIE
“Polysilicon can be etched anisotropically & isotropically in chlorine gas, and it is also very selective to oxide. The table below outlines an isotropic & anisotropic etch recipe using Chlorine chemistry: …” read the full article
RIE Grass
Application: Failure Analysis
“RIE grass is an undesirable artifact of etching which prevents a clean delayering of the integrated circuit and interferes with failure analysis. RIE grass occurs when an etch resistant material accumulates in small patches on the sample surface. These patches cause micro-etch-masking, which results in formation of cones.” read the full article
Silicon Dioxide Etch
Application: Failure Analysis
Trion Tool: Phantom III RIE
“There are many types of silicon dioxide in use today. They all etch in the same chemistry, however the recipes and etch rates vary a little with the type. Typically, highly doped oxides etch faster and oxides with high carbon content etch dirtier. The chemical reaction for this process is given below: …” read the full article
Silicon Nitride Etch
Application: Failure Analysis
Trion Tool: Phantom III RIE
“Silicon nitride typically comprises the final passivation layer of an IC. It etches readily in plasmas that contain a lot of free fluorine (such as SF6/O2 or CF4/O2 plasmas). The SF6 is isotropic by nature. However, in this case, this property is actually advantageous in removing the nitride sidewalls surrounding top metal. The equation for this reaction is: …” read the full article
PAPER: Planar Deprocessing Of Advanced VLSI Devices
By Kendall Scott Wills, Texas Instruments
Application: Failure Analysis
“Problem Statement: To deprocess a VLSI Semiconductor device in order to inspect the longest possible net the surface of the device should remain planar. A working definition of planar is to have only one level of material visible across the entire expanse of the device at a time. There should be no roll off of the layer at the edge or the device. There can be no deprocessing induced artifacts. The deprocessing must not loose the defect, what ever it might be.” read the full article
PAPER: Plasma Delayering of Integrated Circuits
By A. Crockett and M. Almoustafa (Trion Technology) and W. Vanderlinde (Laboratory for Physical Sciences, College Park, MD)
Application: Failure Analysis
“This paper gives a brief introduction to the basic concepts in plasma processing, discusses today’s state-of-the-art techniques for dry processing in failure analysis and provides an outline of dry etch recipes for etching critical layers on new technologies. Also discussed are solutions to the major pit falls of dry etching such as RIE grass and keeping devices active.” read the full article
This paper can also be found at: www.spie.org
PAPER: Rapid Integrated Circuit Delayering Without Grass
By William E. Vanderlinde and Christopher J. Von Benken (Microelectronics Research Laboratory, Columbia, MD) and Addison R. Crockett (Trion Technology)
Application: Failure Analysis
Trion Tool: Minilock-Phantom III RIE
“Failure analysis of integrated circuits (ICs) often requires the selective removal of
materials such as silicon dioxide, silicon nitride, aluminum, polysilicon, titanium and tungsten. Although wet chemical etching is useful in some cases, it lacks the precise control needed to successfully delayer modern ICs. Reactive ion etching (RIE) is used for delayering because…” read the full article
This paper can also be found at: Proc. SPIE Vol. 2874, p. 260-271 bookstore.spie.org
PAPER: Reliability Issues And Advanced Failure Analysis Deprocessing Techniques For Copper/Low-K Technology
By Huixian Wu, James Cargo, Carl Peridier and Joe Serpiello (Agere Systems, IC Quality Organization, Product Analysis Lab, Allentown, PA)
Application: Failure Analysis
Trion Tool: Phantom RIE
Summary: With technology continually scaling down, Cu/low-k technology has been introduced to reduce interconnect resistance, improve electromigration resistance and reduce cross talk effects. In this paper, we discuss new failure modes, reliability issues and failure analysis (FA) challenges for copper technology. Several FA deprocessing techniques are discussed: wet chemical etching, reactive ion etching (RIE), parallel polishing, chemical mechanical polishing (CMP) and a combination of these techniques. Specific details are given of RIE process characterization and optimization for several inter-level dielectrics to attain high etch selectivity, free of RIE grass. We find the combination of CMP and RIE deprocessing techniques works well in most situations for copper technologies. Cross-section analysis of copper devices is also discussed. The development of reproducible backside silicon sample preparation techniques has become increasingly important to accurately localize defects for Cu/low-k technology. Several backside sample preparation techniques are described including mechanical milling, RIE and wet chemical etching. Finally, some FA case studies of Cu/low-k devices are presented.”
ieeexplore.ieee.org/iel5/8520/26927/01197805.pdf
|
